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| 4.8 khz ultralow noise 24-bit sigma-delta adc with pga ad7190 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. mclk1 mclk2 p0/refin2(?) p1/refin2(+) dv dd dgnd refin1(+) refin1(?) ain1 ain2 ain3 ain4 features rms noise: 8.5 nv @ 4.7 hz (gain = 128) 16 noise free bits @ 2.4 khz (gain = 128) up to 22.5 noise free bits (gain = 1) offset drift: 5 nv/c gain drift: 1 ppm/c specified drift over time 2 differential/4 pseudo differential input channels automatic channel sequencer programmable gain (1 to 128) output data rate: 4.7 hz to 4.8 khz internal or external clock simultaneous 50 hz/60 hz rejection 4 general-purpose digital outputs power supply av dd : 4.75 v to 5.25 v dv dd : 2.7 v to 5.25 v current: 6 ma temperature range: C40c to +105c interface 3-wire serial spi, qspi?, microwire?, and dsp compatible schmitt trigger on sclk applications weigh scales strain gauge transducers pressure measurement temperature measurement chromatography plc/dcs analog input modules data acquisition medical and scientific instrumentation general description the ad7190 is a low noise, complete analog front end for high precision measurement applications. it contains a low noise, 24-bit sigma-delta (-) analog to digital converter (adc). the on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the adc. the device can be configured to have two differential inputs or four pseudo differential inputs . the on-chip channel sequencer allows several channels to be enabled, and the ad7190 sequentially converts on each en abled channel. this simplifies communication with the part. the on-chip 4.92 mhz clock can be used as the clock source to the adc or, alternatively, an external clock or crystal can be used. the output data rate from the part can be varied from 4.7 hz to 4.8 khz. the device has two digital filter options. the choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 hz/60 hz rejection. for applications that require all conversions to be settled, the ad7190 includes a zero latency feature. the part operates with 5 v analog power supply and a digital power supply from 2.7 v to 5.25 v. it consumes a current of 6 ma. it is housed in a 24-lead tssop package. functional block diagram a incom bpdsw agnd ad7190 reference detect serial interface and control logic temp sensor clock circuitry av dd agnd dout/rdy din sclk cs sync p3 p2 - adc pga mux 07640-001 figure 1.
ad7190 rev. 0 | page 2 of 40 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ................................................................ 7 ? circuit and timing diagrams ..................................................... 7 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configuration and function descriptions ........................... 10 ? typical performance characteristics ........................................... 12 ? rms noise and resolution ............................................................ 15 ? sinc 4 chop disabled ................................................................... 15 ? sinc 3 chop disabled ................................................................... 16 ? sinc 4 chop enabled .................................................................... 17 ? sinc 3 chop enabled .................................................................... 18 ? on-chip registers .......................................................................... 19 ? communications register ......................................................... 19 ? status register ............................................................................. 20 ? mode register ............................................................................. 20 ? configuration register .............................................................. 22 ? data register ............................................................................... 24 ? gpocon register ..................................................................... 24 ? offset register ............................................................................. 25 ? full-scale register ...................................................................... 25 ? adc circuit information .............................................................. 26 ? overview ..................................................................................... 26 ? filter, output data rate, settling time ................................... 26 ? digital interface .......................................................................... 29 ? circuit description......................................................................... 33 ? analog input channel ............................................................... 33 ? pga .............................................................................................. 33 ? bipolar/unipolar configuration .............................................. 33 ? data output coding .................................................................. 33 ? clock ............................................................................................ 33 ? burnout currents ....................................................................... 34 ? reference ..................................................................................... 34 ? reference detect ......................................................................... 34 ? reset ............................................................................................. 34 ? system synchronization ............................................................ 35 ? temperature sensor ................................................................... 35 ? bridge power-down switch ...................................................... 35 ? logic outputs ............................................................................. 35 ? enable parity ............................................................................... 35 ? calibration ................................................................................... 36 ? grounding and layout .............................................................. 36 ? applications information .............................................................. 38 ? weigh scales ................................................................................ 38 ? outline dimensions ....................................................................... 39 ? ordering guide .......................................................................... 39 ? revision history 10/08revision 0initial version ad7190 rev. 0 | page 3 of 40 specifications av dd = 4.75 v to 5.25 v; dv dd = 2.7 v to 5.25 v; gnd = 0 v; refin1(+) = av dd ; refin1(?) = gnd; mclk = 4.92 mhz; all specifications t min to t max , unless otherwise noted. table 1. parameter ad7190b unit test conditions/comments 1 adc output data rate 4.7 to 4800 hz nom chop disabled. 1.17 to 1200 hz nom chop enabled. no missing codes 2 24 bits min fs > 1, sinc 4 filter. 24 bits min fs > 4, sinc 3 filter. resolution see the rms noise and resolution section rms noise and output data rates see the rms noise and resolution section integral nonlinearity 5 ppm of fsr max 1 ppm typical, gain = 1. 15 ppm of fsr max 5 ppm typical, gain > 1. offset error 3 75/gain v typ chop disabled. 0.5 v typ chop enabled. offset error drift vs. temperature 100/gain nv/c typ gain = 1 to 16. chop disabled. 5 nv/c typ gain = 32 to 128. chop disabled. 5 nv/c typ chop enabled. offset error drift vs. time 25 nv/1000 hours typ gain 32 gain error 3 , 4 0.005 % max 0.001 % typical, gain = 1, av dd = 5 v. 0.0075 % typ gain > 1, post internal-calibration. gain drift vs. temperature 1 ppm/c typ gain drift vs. time 10 ppm/1000 hours typ gain = 1. power supply rejection 95 db typ gain = 1, v in = 1 v. 95 db min gain > 1, v in = 1 v/gain. 110 db typical. common-mode rejection @ dc 100 db min gain = 1, v in = 1 v 2 110 db min gain > 1, v in = 1 v/gain. @ 50 hz, 60 hz 2 120 db min 10 hz output data rate, 50 1 hz, 60 1 hz. @ 50 hz, 60 hz 2 120 db min 50 1 hz (50 hz output data rate), 60 1 hz (60 hz output data rate). normal mode rejection 2 sinc 4 filter internal clock @ 50 hz, 60 hz 100 db min 10 hz output data rate, 50 1 hz, 60 1 hz. 74 db min 50 hz output data rate, rej60 5 = 1, 50 1 hz, 60 1 hz. @ 50 hz 96 db min 50 hz output data rate, 50 1 hz. @ 60 hz 97 db min 60 hz output data rate, 60 1 hz. ad7190 rev. 0 | page 4 of 40 parameter ad7190b unit test conditions/comments 1 external clock @ 50 hz, 60 hz 120 db min 10 hz output data rate, 50 1 hz, 60 1 hz. 82 db min 50 hz output data rate, rej60 5 = 1, 50 1 hz, 60 1 hz. @ 50 hz 120 db min 50 hz output data rate, 50 1 hz. @ 60 hz 120 db min 60 hz output data rate, 60 1 hz. sinc 3 filter internal clock @ 50 hz, 60 hz 75 db min 10 hz output data rate, 50 1 hz, 60 1 hz. 60 db min 50 hz output data rate, rej60 5 = 1, 50 1 hz, 60 1 hz. @ 50 hz 72 db min 50 hz output data rate, 50 1 hz. @ 60 hz 72 db min 60 hz output data rate, 60 1 hz. external clock @ 50 hz, 60 hz 100 db min 10 hz output data rate, 50 1 hz, 60 1 hz. 67 db min 50 hz output data rate, rej60 5 = 1, 50 1 hz, 60 1 hz. @ 50 hz 100 db min 50 hz output data rate, 50 1 hz. @ 60 hz 100 db min 60 hz output data rate, 60 1 hz. analog inputs differential input voltage ranges v ref /gain v nom v ref = refinx(+) ? refinx(?), gain = 1 to 128. (av dd C 1.25 v)/gain v min/max gain > 1. absolute ain voltage limits 2 unbuffered mode gnd ? 50 mv v min av dd + 50 mv v max buffered mode gnd + 250 mv v min av dd ? 250 mv v max analog input current buffered mode input current 2 2 na max gain = 1. 3 na max gain > 1. input current drift 5 pa/c typ unbuffered mode input current 5 a/v typ gain = 1, input curren t varies with input voltage. 1 a/v typ gain > 1. input current drift 0.05 na/v/c typ external clock. 1.6 na/v/c typ internal clock. reference input refin voltage av dd v nom refin = refinx(+) ? refinx(?). reference voltage range 2 1 v min av dd v max the differential input must be limited to (av dd C 1.25 v)/gain when gain > 1. absolute refin voltage limits 2 gnd C 50 mv v min av dd + 50 mv v max average reference input current 7 a/v typ average reference input current drift 0.03 na/v/c typ external clock. 1.3 na/v/c typ internal clock. ad7190 rev. 0 | page 5 of 40 parameter ad7190b unit test conditions/comments 1 normal mode rejection 2 same as for analog inputs common-mode rejection 100 db typ reference detect levels 0.3 v min 0.6 v max temperature sensor accuracy 2 c typ applies after user calibration at one temperature. sensitivity 2815 codes/c typ bipolar mode. bridge power-down switch r on 10 max allowable current 2 30 ma max continuous current. burnout currents ain current 500 na nom analog inputs must be buffered and chop disabled. digital outputs (p0 to p3) output high voltage, voh 2 4 v min av dd = 5v, i source = 200 a. output low voltage, vol 2 0.4 v max av dd = 5v, i sink = 800 a. floating-state leakage current 100 na max floating-state output capacitance 10 pf typ internal/external clock internal clock frequency 4.92 4% mhz min/max duty cycle 50:50 % typ external clock/crystal 2 frequency 4.9152 mhz nom 2.4576/5.12 mhz min/max input low voltage, vinl 0.8 v max dv dd = 5 v. 0.4 v max dv dd = 3 v. input high voltage, vinh 2.5 v min dv dd = 3 v. 3.5 v min dv dd = 5 v. input current 10 a max logic inputs input high voltage, vinh 2 2 v min input low voltage, vinl 2 0.8 v max hysteresis 2 0.1/0.25 v min/v max input currents 10 a max logic output (dout/ rdy ) output high voltage, voh 2 dv dd ? 0.6 v min dv dd = 3 v, i source = 100 a. output low voltage, vol 2 0.4 v max dv dd = 3 v, i sink = 100 a. output high voltage, voh 2 4 v min dv dd = 5 v, i source = 200 a. output low voltage, vol 2 0.4 v max dv dd = 5 v, i sink = 1.6 ma. floating-state leakage current 10 a max floating-state output capacitance 10 pf typ data output coding offset binary system calibration 2 full-scale calibration limit 1.05 fs v max zero-scale calibration limit ?1.05 fs v min input span 0.8 fs v min 2.1 fs v max ad7190 rev. 0 | page 6 of 40 parameter ad7190b unit test conditions/comments 1 power requirements 6 power supply voltage av dd ? agnd 4.75/5.25 v min/max dv dd ? dgnd 2.7/5.25 v min/max power supply currents ai dd current 1 ma max 0.85 ma typical, gain = 1, buffer off. 1.3 ma max 1.1 ma typical, gain = 1, buffer on. 4.5 ma max 3.5 ma typical, gain = 8, buffer off. 4.75 ma max 4 ma typical, gain = 8, buffer on. 6.2 ma max 5 ma typical, gain = 16 to 128, buffer off. 6.75 ma max 5.5 ma typical, gain = 16 to 128, buffer on. di dd current 0.4 ma max 0.35 ma typical, dv dd = 3 v. 0.6 ma max 0.5 ma typical, dv dd = 5 v. 1.5 ma typ external crystal used. i dd (power-down mode) 2 a max 1 temperature range: ?40c to +105c. 2 specification is not production tested but is supported by characterization data at initial product release. 3 following a system or internal zero-scale calibration, the offset erro r is in the order of the no ise for the pro grammed gain a nd output data rate selected. a system full- scale calibration reduces the gain erro r to the order of the no ise for the programmed gain and output data rate. 4 full-scale error applies to both positive and negative full scale and applies at the fact ory calibration conditions (av dd = 5 v, gain = 1, t a = 25 c ). 5 rej60 is a bit in the mode register. when the output data rate is set to 50 hz, setting rej60 to 1 places a notch at 60 hz, al lowing simultaneous 50 hz/60 hz rejection. 6 digital inputs equal to dv dd or gnd. ad7190 rev. 0 | page 7 of 40 timing characteristics av dd = 4.75 v to 5.25 v; dv dd = 2.7 v to 5.25 v; gnd = 0 v, input logic 0 = 0 v, input logic 1 = dv dd , unless otherwise noted. table 2. parameter limit at t min , t max (b version) unit conditions/comments 1 , 2 t 3 100 ns min sclk high pulse width t 4 100 ns min sclk low pulse width read operation t 1 0 ns min cs falling edge to dout/ rdy active time 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 2 3 0 ns min sclk active edge to data valid delay 4 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 5 5 , 6 10 ns min bus relinquish time after cs inactive edge 80 ns max t 6 0 ns min sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/ rdy high write operation t 8 0 ns min cs falling edge to sclk active edge setup time 4 t 9 30 ns min data valid to sclk edge setup time t 10 25 ns min data valid to sclk edge hold time t 11 0 ns min cs rising edge to sclk edge hold time 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.6 v. 2 see figure 3 and figure 4. 3 these numbers are measured with the load ci rcuit shown in figure 2 and defined as the time required for the output to cross th e v ol or v oh limits. 4 the sclk active edge is the falling edge of sclk. 5 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit shown i n figure 2. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times quote d in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 rdy returns high after a read of the data register. in single conversion mode and continuous conversion mode, the same data can be read again, if required, while rdy is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. if the con tinuous read feature is enabled, the digital word can be read only once. circuit and timing diagrams i sink (1.6ma with dv dd = 5v, 100a with dv dd = 3v) i source (200a with dv dd = 5v, 100a with dv dd = 3v) 1.6v to output pin 50pf 0 7640-002 figure 2. load circuit for timing characterization ad7190 rev. 0 | page 8 of 40 t 4 t 2 t 3 t 1 t 6 t 5 t 7 cs (i) dout/rdy (o) sclk (i) i = input, o = output msb lsb 0 7640-003 figure 3. read cycle timing diagram i = input, o = output cs (i) s clk (i) din (i) msb lsb t 8 t 9 t 10 t 11 0 7640-004 figure 4. write cycle timing diagram ad7190 rev. 0 | page 9 of 40 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd ? 0.3 v to +6.5 v dv dd to gnd ? 0.3 v to +6.5 v analog input voltage to gnd ? 0.3 v to av dd + 0.3 v reference input voltage to gnd ? 0.3 v to av dd + 0.3 v digital input voltage to gnd ? 0.3 v to dv dd + 0.3 v digital output voltage to gnd ? 0.3 v to dv dd + 0.3 v ain/digital input current 10 ma operating temperature range ?40c to +105c storage temperature range ?65c to +150c maximum junction temperature 150c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jc unit 24-lead tssop 97.9 14 c/w esd caution ad7190 rev. 0 | page 10 of 40 nc = no connect pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 mclk2 sclk cs p1/refin2(+) p2 p3 mclk1 p0/refin2(?) nc aincom 12 11 ain2 ain1 20 21 22 23 24 19 18 17 16 15 dout/rdy sync dv dd agnd dgnd av dd bpdsw refin1(?) refin1(+) din ad7190 top view (not to scale) 14 13 ain3 ain4 07640-005 figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 mclk1 when the master clock for the device is provided exte rnally by a crystal, the crystal is connected between mclk1 and mclk2. 2 mclk2 master clock signal for the device. the ad7190 has an internal 4.92 mhz clock. th is internal clock can be made available on the mclk2 pin. the clock for the ad 7190 can be provided externally also in the form of a crystal or external clock. a crystal can be tied across the mclk1 and mclk2 pins. alternatively, the mclk2 pin can be driven with a cmos-compatible clock and the mclk1 pin left unconnected. 3 sclk serial clock input. this serial cloc k input is for data transfers to and from the adc. the sclk has a schmitt- triggered input, making the interface suitable for opto-isolated applications. the serial clock can be continuous with all data transmitte d in a continuous train of pulses. alternatively, it can be a noncon- tinuous clock with the information transmitted to or from the adc in smaller batches of data. 4 cs chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. cs can be hardwired low, allowing the adc to operate in 3-wire mode with sclk, din, and dout used to interface with the device. 5 p3 digital output pin. this pin can function as a general-purpose output bit referenced between av dd and agnd. 6 p2 digital output pin. this pin can function as a general-purpose output bit referenced between av dd and agnd. 7 p1/refin2(+) digital output pin/positive reference input. this pin functions as a general-purpose output bit referenced between av dd and agnd. when refsel = 1, this pin functions as refin2(+). an external reference can be applied between refin2(+) and refin2(?). refin2(+) can lie anywhere between av dd and gnd + 1 v. the nominal reference voltage, (refin2(+) ? refin2(?)), is av dd , but the part functions with a reference from 1 v to av dd . 8 p0/refin2(?) digital output pin/negative reference input. this pin functions as a general-purpose output bit referenced between av dd and agnd. when refsel = 1, this pin function s as refin2(?). this reference input can lie anywhere between gnd and av dd ? 1 v. 9 nc no connect. this pin should be tied to agnd. 10 aincom analog input ain1 to analog inp ut ain4 are referenced to this in put when configured for pseudo differential operation. 11 ain1 analog input. it can be configured as the positive input of a fully diffe rential input pair when used with ain2 or as a pseudo differential input when used with aincom. 12 ain2 analog input. it can be configured as the negative in put of a fully differential input pair when used with ain1 or as a pseudo differential input when used with aincom. ad7190 rev. 0 | page 11 of 40 pin no. mnemonic description 13 ain3 analog input. it can be configured as the positive inp ut of a fully differential input pair when used with ain4 or as a pseudo differential input when used with aincom. 14 ain4 analog input. it can be configured as the negative in put of a fully differential input pair when used with ain3 or as a pseudo differentia l input when used with aincom. 15 refin1(+) positive reference input. an external reference can be applied between refin1(+) and refin1(?). refin1(+) can lie anywhere between av dd and gnd + 1 v. the nominal reference voltage, (refin1(+) ? refin1(?)), is av dd , but the part functions with a reference from 1 v to av dd . 16 refin1(?) negative reference input. this reference input can lie anywhere between gnd and av dd ? 1 v. 17 bpdsw bridge power-down switch to agnd. 18 agnd analog ground reference point. 19 dgnd digital ground reference point. 20 av dd analog supply voltage, 4.75 v to 5.25 v. av dd is independent of dv dd . 21 dv dd digital supply voltage, 2.7 v to 5.25 v. dv dd is independent of av dd . 22 sync logic input that allows for synchronization of the digital filters and analog modulators when using multiple ad7190 devices. while sync is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is held in its reset state. sync does not affect the digital interface but does reset rdy to a high state if it is low. sync has a pull-up resistor internally to dv dd . 23 dout/ rdy serial data output/data ready output. dout/ rdy serves a dual purpose. it functions as a serial data output pin to access the output shift register of the ad c. the output shift register can contain data from any of the on-chip data or control registers. in addition, dout/ rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge can be used as an interrupt to a processor, indicating that valid data is availa ble. with an external serial cloc k, the data can be read using the dout/ rdy pin. with cs low, the data/control word info rmation is placed on the dout/ rdy pin on the sclk falling edge and is vali d on the sclk rising edge. 24 din serial data input to the input shift register on the ad c. data in this shift register is transferred to the control registers in the adc, with the register selection bits of the communications register identifying the appropriate register. ad7190 rev. 0 | page 12 of 0 200 400 600 800 1000 sample typical performance characteristics 8,388,760 8,388,758 8,388,756 8,388,754 8,388,752 8,388,750 8,388,748 8,388,746 code 40 07640-106 8, 8, 8, 8, 8, 8, 8, 8, code figure 6. noise (v ref = 5 v, output data rate = 4.7 hz, gain = 128, chop disabled, sinc 4 filter) 07640-10 8,388,950 8,388,900 8,388,800 8,388,750 8,388,650 8,388,600 8,388,850 8,388,700 8,388,550 8,388,500 8,388,450 0 200 400 600 800 1000 100 300 500 700 900 code samples 7 07640-108 30 20 25 15 10 5 0 8,388,490 8,388,576 8,388,662 8,388,748 8,388,834 8,388,920 frequency code figure 8. noise (v ref = 5 v, output data rate = 4800 hz, gain = 128, chop disabled, sinc 4 filter) 250 200 150 100 50 0 388,746 388,748 388,750 388,752 388,754 388,756 388,758 388,760 frequency 07640-109 figure 9. noise distribution histogram (v ref = 5 v, output data rate = 4800 hz, gain = 128, chop disabled, sinc 4 filter) figure 7. noise distribution histogram (v ref = 5 v, output data rate = 4.7 hz, gain = 128, chop disabled, sinc 4 filter) ad7190 rev. 0 | page 13 of 8,388,820 8,388,800 8,388,760 8,388,740 8,388,700 8,388,680 8,388,780 8,388,720 8,388,660 8,388,640 8,388,620 0 200 400 600 800 1000 100 300 500 700 900 code samples 40 07640-110 8,388,620 8,388,660 8,388,700 8,388,740 8,388,780 8,388,820 code figure 10. noise (v ref = 5 v, output data rate = 4800 hz, gain = 1, chop disabled, sinc 4 filter) 80 50 70 40 60 30 20 10 0 frequency 0 7640-111 3.0 2.0 1.0 0 ?1.0 ?2.0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 inl (ppm of fsr) v in (v) 07640-112 6 4 2 0 ?2 ?4 ?6 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 inl (ppm of fsr) v in (v) figure 11. noise distribution histogram (v ref = 5 v, output data rate = 4800 hz, gain = 1, chop disabled, sinc 4 filter) figure 12. inl (gain = 1) 07640-113 figure 13. inl (gain = 128) ad7190 rev. 0 | page 14 54 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) of 40 66 64 62 60 58 56 output voltage (v) 07640-114 ?0.7 ?60 ?40 ?20 0 20 40 60 80 100 120 temerature (c) 07640-115 1.000008 1.000007 1.000006 1.000005 1.000004 1.000003 1.000002 1.000001 1.000000 ?60 ?40 ?20 0 20 40 60 80 100 120 gain temperature (c) 07640-116 128.003 128.002 128.001 128.000 127.999 127.998 127.997 127.996 gain figure 14. offset error (gain = 1, chop disabled) figure 16. gain error (gain = 1, chop disabled) 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 offset (v) ?60 ?40 ?20 0 20 40 60 80 100 120 temperature (c) 07640-117 figure 15. offset error (gain = 128, chop disabled) figure 17. gain error (gain = 128, chop disabled) ad7190 rev. 0 | page 15 of 40 rms noise and resolution the ad7190 has a choice of two filter types: sinc 4 and sinc 3 . in addition, the ad7190 can be operated with chop enabled or chop disabled. the following tables show the rms noise of the ad7190 for some of the output data rates and gain settings with chop disabled and enabled for the sinc 4 and sinc 3 filters. the numbers given are for the bipolar input range with the external 5 v reference. these numbers are typical and are generated with a differential input voltage of 0 v when the adc is continuously converting on a single channel. the effective resolution is also shown, and the output peak-to-peak (p-p) resolution, or noise-free resol- ution, is listed in parentheses. it is important to note that the effective resolution is calculated using the rms noise, wheras the p-p resolution is calculated based on peak-to-peak noise. the p- p resolution represents the resolution for which there is no code flicker. these numbers are typical and are rounded to the nearest ? lsb. sinc 4 chop disabled table 6. rms noise (nv) vs. ga in and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 1023 4.7 852.5 250 38 21 12 10 8.5 640 7.5 533 310 45 25 16 12 10.5 480 10 400 330 50 30 18 14 11.5 96 50 800 900 125 78 45 33 28 80 60 66.7 970 140 88 52 36 31 32 150 26.7 1460 215 125 75 55 48 16 300 13.3 1900 285 170 100 75 67 5 960 4.17 3000 480 280 175 140 121 2 2400 1.67 5000 780 440 280 220 198 1 4800 0.83 14,300 1920 1000 550 380 295 table 7. effective resolution (peak-to-peak resolution) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 gain of 8 1 gain of 16 1 gain of 32 1 gain of 64 1 gain of 128 1 1023 4.7 852.5 24 (22.5) 24 (22) 24 (22) 24 (22) 24 (21) 23 (20.5) 640 7.5 533 24 (22) 24 (22) 24 (22) 24 (21.5) 23.5 (21) 23 (20) 480 10 400 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23.5 (20.5) 22.5 (20) 96 50 800 23.5 (20.5) 23.5 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 80 60 66.7 23.5 (20.5) 23 (20.5) 22.5 ( 20) 22.5 (20) 22 (19.5) 21.5 (18.5) 32 150 26.7 22.5 (20) 22.5 (19.5) 22.5 (19. 5) 22 (19.5) 21.5 (18.5) 20.5 (18) 16 300 13.3 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (19) 21 (18.5) 20 (17.5) 5 960 4.17 21.5 (19) 21.5 (18.5) 21 (18. 5) 21 (18) 20 (17.5) 19.5 (16.5) 2 2400 1.67 21 (18) 20.5 (18) 20.5 (17.5) 20 (17.5) 19.5 (16.5) 18.5 (16) 1 4800 0.83 19.5 (16.5) 19.5 (16.5) 19.5 ( 16.5) 19 (16.5) 18.5 (16) 18 (15.5) 1 the output peak-to-peak (p-p) resolution is listed in parentheses. ad7190 rev. 0 | page 16 of 40 sinc 3 chop disabled table 8. rms noise (nv) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 1023 4.7 639.4 270 42 23 13.5 10.5 9 640 7.5 400 320 50 27 17 13 11.5 480 10 300 350 60 35 19 15 12.5 96 50 60 1000 134 86 50 35 29 80 60 50 1050 145 95 55 40 32 32 150 20 1500 225 130 80 58 50 16 300 10 1950 308 175 110 83 73 5 960 3.125 4000 590 330 200 150 133 2 2400 1.25 56,600 7000 3500 1800 900 490 1 4800 0.625 442,000 55,000 28,000 14,000 7000 3450 table 9. effective resolution (peak-to-peak resolution) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 gain of 8 1 gain of 16 1 gain of 32 1 gain of 64 1 gain of 128 1 1023 4.7 639.4 24 (22.5) 24 (22) 24 (22) 24 (21.5) 24 (21) 23 (20.5) 640 7.5 400 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20) 480 10 300 24 (22) 24 (21.5) 24 (21.5) 24 (21) 23.5 (20.5) 22.5 (20) 96 50 60 23.5 (20.5) 23 (20.5) 23 (20) 22.5 (20) 22 (19.5) 21.5 (18.5) 80 60 50 23 (20.5) 23 (20.5) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5) 32 150 20 22.5 (20) 22.5 (19.5) 22 (19.5) 22 (19) 21.5 (18.5) 20.5 (18) 16 300 10 22.5 (19.5) 22 (19) 22 (19) 21.5 (18.5) 21 (18) 20 (17.5) 5 960 3.125 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17.5) 19 (16.5) 2 2400 1.25 17.5 (14.5) 17.5 (14.5) 17.5 (14. 5) 17.5 (14.5) 17.5 (14.5) 17.5 (14.5) 1 4800 0.625 14.5 (11.5) 14.5 (11.5) 14.5 (11. 5) 14.5 (11.5) 14.5 (11.5) 14.5 (11.5) 1 the output peak-to-peak (p-p) resolution is listed in parentheses. ad7190 rev. 0 | page 17 of 40 sinc 4 chop enabled table 10. rms noise (nv) vs. ga in and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 1023 1.175 1702 177 27 15 8.5 7 6 640 1.875 1067 219 32 18 11.5 8.5 7.5 480 2.5 800 234 36 21 13 10 8.5 96 12.5 160 637 89 55 32 24 20 80 15 133 686 99 63 37 26 22 32 37.5 53 1033 152 89 53 39 34 16 75 26.7 1343 202 120 71 53 48 5 240 8.33 2121 340 198 124 99 86 2 600 3.33 3536 552 311 198 156 140 1 1200 1.67 10,200 1360 707 389 26 209 table 11. effective resolution (peak-to-peak resolution) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 gain of 8 1 gain of 16 1 gain of 32 1 gain of 64 1 gain of 128 1 1023 1.175 1702 24 (23) 24 (22.5) 24 (22.5) 24 (22.5) 24 (21.5) 23.5 (21) 640 1.875 1067 24 (22.5) 24 (22.5) 24 (22.5) 24 (22) 24 (21.5) 23.5 (20.5) 480 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21) 23 (20.5) 96 12.5 160 24 (21) 24 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 80 15 133 24 (21) 23.5 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 32 37.5 53 23 (20.5) 23 (20) 23 (20) 22.5 (20) 22 (19) 21 (18.5) 16 75 26.7 23 (20) 22.5 (20) 22.5 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 5 240 8.33 22 (19.5) 22 (19) 21.5 (19) 21.5 (18.5) 20.5 (18) 20 (17) 2 600 3.33 21.5 (18.5) 21 (18.5) 21 (18) 20.5 (18) 20 (17) 19 (16.5) 1 1200 1.67 20 (17) 20 (17) 20 (17) 19.5 (17) 19 (16.5) 18.5 (16) 1 the output peak-to-peak (p-p) resolution is listed in parentheses. ad7190 rev. 0 | page 18 of 40 sinc 3 chop enabled table 12. rms noise (nv) vs. ga in and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 1023 1.56 1282 191 30 16.5 10 8 6.5 640 2.5 800 226 36 19 12 9 8.5 480 3.33 600 248 43 25 14 11 9 96 16.6 120 708 95 61 36 25 21 80 20 100 743 103 68 39 29 23 32 50 40 1061 159 92 57 41 36 16 100 20 1380 218 124 78 59 52 5 320 6.25 2829 418 234 142 106 94 2 800 2.5 40,100 4950 2475 1273 637 347 1 1600 1.25 312,550 38,540 19,800 9900 4950 2440 table 13. effective resolution (peak-to-peak resolution) vs. gain and output data rate filter word (decimal) output data rate (hz) settling time (ms) gain of 1 1 gain of 8 1 gain of 16 1 gain of 32 1 gain of 64 1 gain of 128 1 1023 1.56 1282 24 (23) 24 (22.5) 24 (22. 5) 24 (22) 24 (21.5) 23.5 (21) 640 2.5 800 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21.5) 23 (20.5) 480 3.33 600 24 (22.5) 24 (22) 24 ( 22) 24 (21.5) 24 (21) 23 (20.5) 96 16.6 120 24 (21) 23.5 (21) 23.5 (20.5) 23 (20.5) 22.5 (20) 22 (19) 80 20 100 23.5 (21) 23.5 (21) 23 (20.5) 23 (20) 22.5 (19.5) 21.5 (19) 32 50 40 23 (20.5) 23 (20) 22.5 (20) 22.5 (19.5) 22 (19) 21 (18.5) 16 100 20 23 (20) 22.5 (19.5) 22.5 (19.5) 22 (19) 21.5 (18.5) 20.5 (18) 5 320 6.25 22 (19) 21.5 (19) 21.5 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 2 800 2.5 18 (15) 18 (15) 18 ( 15) 18 (15) 18 (15) 18 (15) 1 1600 1.25 15 (12) 15 (12.5) 15 ( 12) 15 (12) 15 (12) 15 (12) 1 the output peak-to-peak (p-p) resolution is listed in parentheses. ad7190 rev. 0 | page 19 of 40 on-chip registers the adc is controlled and configured via a number of on-chip registers, which are described in the following sections. in the descriptions, set implies a logic 1 state and cleared implies a logic 0 state, unless otherwise noted. communications register (rs2, rs1, rs0 = 0, 0, 0) the communications register is an 8-bit write-only register. all communications to the part must start with a write operation to the communications register. the data written to the communi- cations register determines whether the next operation is a read or write operation and in which register this operation takes place. for read or write operations, when the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. this is the default state of the interface and, on power-up or after a reset, the adc is in this default state waiting for a write operation to the communi- cations register. in situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with din high returns the adc to this default state by resetting the entire part. table 14 outlines the bit designations for the communications register. cr0 through cr7 indicate the bit locations, cr denoting that the bits are in the communications register. cr7 denotes the first bit of the data stream. the number in parentheses indicates the power-on/reset default status of that bit. cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 wen (0) r/ w (0) rs2(0) rs1(0) rs0(0) cread(0) 0(0) 0(0) table 14. communications register bit designations bit location bit name description cr7 wen write enable bit. a 0 must be written to this bit for a write to the communications register to occur. if a 1 is the first bit written, the part does not clock on to subseq uent bits in the register. it stays at this bit location until a 0 is written to this bit. after a 0 is written to the wen bit, the next seven bits are loaded to the communications register. cr6 r/ w a 0 in this bit location indicates that the next operatio n is a write to a specified register. a 1 in this position indicates that the next operation is a read from the designated register. cr5 to cr3 rs2 to rs0 register address bits. these address bits are used to select which registers of the adc are selected during the serial interface communication. see table 15 . cr2 cread continuous read of the data register. when this bit is se t to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the dout pin when the sclk pulses are applied after the rdy pin goes low to indicate that a conversion is complete. the communications register does not have to be written to for subsequent data reads. to enable continuous read, the instruction 01011100 must be written to the communications register. to disable continuo us read, the instruction 01011000 must be written to the communications register while the rdy pin is low. while continuous read is enabled, the adc monitors activity on the din line so that it can receive the inst ruction to disable continuous read. additionally, a reset occurs if 40 consecutive 1s are seen on din. therefore, din should be held low until an instruction is to be written to the device. cr1 to cr0 these bits must be programmed to logic 0 for correct operation. table 15. register selection rs2 rs1 rs0 register register size 0 0 0 communications register during a write operation 8 bits 0 0 0 status register during a read operation 8 bits 0 0 1 mode register 24 bits 0 1 0 configuration register 24 bits 0 1 1 data register/data register plus status information 24 bits/32 bits 1 0 0 id register 8 bits 1 0 1 gpocon register 8 bits 1 1 0 offset register 24 bits 1 1 1 full-scale register 24 bits ad7190 rev. 0 | page 20 of 40 status register (rs2, rs1, rs0 = 0, 0, 0; power-on/reset = 0x80) the status register is an 8-bit, read-only register. to access the adc status register, the user must write to the communicatio ns register, select the next operation to be a read, and load bit rs2, bit rs1, and bit rs0 with 0. tabl e 16 outlines the bit designations for the status register. sr0 through sr7 indicate the bit locations, sr denoting that the bits are in the status register. sr7 denotes the fir st bit of the data stream. the number in parentheses indicates the power-on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) noref(0) parity(0) chd3(0) chd2(0) chd1(0) chd0(0) table 16. status register bit designations bit location bit name description sr7 rdy ready bit for the adc. cleared when data is written to the adc data register. the rdy bit is set automatically after the adc data register is read, or after a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. it is also set when the part is placed in power-down mode or idle mode or when sync is taken low. the end of a conversion is also indicated by the dout/ rdy pin. this pin can be used as an alternative to the status register for monitoring the adc for conversion data. sr6 err adc error bit. this bit is written to at the same time as the rdy bit. the err bit is set to indicate that the result written to the adc data register is clamped to all 0s or all 1s. error sources include overrange or underrange or the absence of a reference voltage. the bit is cleared by a write operation to start a conversion. sr5 noref no external reference bit. this bit is set to indicate that the selected reference (refin1 or refin2) is at a voltage that is below a specified threshold. when set, conversion results are clamped to all 1s. this bit is cleared to indicate that a valid reference is applied to the selected reference pins. the noref bit is enabled by setting the refdet bit in the configuration register to 1. the err bit is also set if the voltage applied to the selected reference input is invalid. sr4 parity parity check of the data register. if the enpar bit in the mo de register is set, the parity bit is set if there is an odd number of 1s in the data register. it is cleared if there is an even nu mber of 1s in the data register. the dat_sta bit in the mode register should be set when th e parity check is used. when the dat_sta bit is set, the contents of the status register are transmitted along with the data for each data register read. sr3 to sr0 chd3 to chd0 these bits indicate which channel corresponds to the data register contents. they do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated. mode register (rs2, rs1, rs0 = 0, 0, 1; power-on/reset = 0x080060) the mode register is a 24-bit register from which data can be read or to which data can be written. this register is used to se lect the operating mode, the output data rate, and the clock source. table 17 outlines the bit designations for the mode register. mr0 through mr23 indicate the bit locations, mr denoting that the bits are in the mode register. mr23 denotes the first bit of the data str eam. the number in parentheses indicates the power-on/reset default status of that bit. any write to the mode register resets the modula tor and filter and sets the rdy bit. mr23 mr22 mr21 mr20 mr19 mr18 mr17 mr16 md2(0) md1(0) md0(0) dat_sta(0) clk1(1) clk0(0) 0 0 mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 sinc3(0) 0 enpar(0) 0 single(0) rej60(0) fs9(0) fs8(0) mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 fs7(0) fs6(1) fs5(1) fs4(0) f s3(0) fs2(0) fs1(0) fs0(0) ad7190 rev. 0 | page 21 of 40 table 17. mode register bit designations bit location bit name description mr23 to mr21 md2 to md0 mode select bits. thes e bits select the operating mode of the ad7190 (see table 18 ). mr20 dat_sta this bit enables the transmission of status regist er contents after each data register read. when dat_sta is set, the contents of the status register are transmitted along with each data register read. this function is useful when several channels are se lected because the status register identifies the channel to which the data register value corresponds. mr19 to mr18 clk1 to clk0 these bits are used to select the clock source for the ad7190. either the on-chip 4.92 mhz clock or an external clock can be used. the ability to use an external clock allows several ad7190 devices to be synchronized. also, 50 hz/60 hz rejection is improved when an accurate external clock drives the ad7190. clk1 clk0 adc clock source 0 0 external crystal used. the external crystal is connected from mclk1 to mclk2. 0 1 external clock used. the external clock is applied to the mclk2 pin. 1 0 internal 4.92 mhz clock. pin mclk2 is tristated. 1 1 internal 4.92 mhz clock. the internal clock is available on mclk2. mr17 to mr16 these bits must be progra mmed with a logic 0 for correct operation. mr15 sinc3 sinc 3 filter select bit. when this bit is cleared, the sinc 4 filter is used (default valu e). when this bit is set, the sinc 3 filter is used. the benefit of the sinc 3 filter compared to the sinc 4 filter is its lower settling time when chop is disabled. for a given output data rate, f adc , the sinc 3 filter has a settling time of f adc /3 while the sinc 4 filter has a settling time of f adc /4. the sinc 4 filter, due to its deeper notches, gives better 50 hz/60 hz rejection. at low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. at higher output data rates (fs values less than 5), the sinc 4 filter gives better performance than the sinc 3 filter for rms noise and no missing codes. mr14 this bit must be programmed with a logic 0 for correct operation. mr13 enpar enable parity bit. when enpar is set, parity checki ng on the data register is enabled. the dat_sta bit in the mode register should be set when the parity check is used. when the dat_sta bit is set, the contents of the status register are transmitted al ong with the data for each data register read. mr12 this bit must be programmed with a logic 0 for correct operation. mr11 single single cycle conversion enable bit. when this bit is set, the ad7190 settles in one conversion cycle so that it functions as a zero latency adc. this bit ha s no affect when multiple analog input channels are enabled or when the single conversion mode is selected. mr10 rej60 this bit enables a notch at 60 hz when the output data rate is equal to 50 hz. the bit should only be set when chop is disabled and when the device is operating with the zero latency function disabled. this bit allows simultaneous 50 hz/60 hz rejection. mr9 to mr0 fs9 to fs0 filter output data rate select bits. the 10 bits of da ta programmed into these bits determine the filter cutoff frequency, the position of the first notch of th e filter, and the output data rate for the part. in association with the gain selection, it also deter mines the output noise (and, therefore, the effective resolution) of the device. when chop is disabled and continuous conversion mode is selected, the first notch of the filter occurs at a freq uency determined by the relationship: filter first notch frequency = ( f mod /64)/ fs where fs is the decimal equivalent of the code in the fs0 to fs9 bits and is in the range 1 to 1023, and fmod is the modulator frequency, which is equal to mclk/16. with a nominal mclk of 4.92 mhz, this results in a first notch frequency range from 4.69 hz to 4.8 khz. changing the filter notch frequency or changing the gain impacts resolution. table 6 through table 13 show the effect of the filter notch frequency an d gain on the effective resolution of the ad7190. the output data rate (or effective conversion time) fo r the device is equal to the frequency selected for the first notch of the filter. for example, if the first no tch of the filter is selected at 50 hz, a new word is available at a 50 hz rate or every 20 ms. when chop is enabled, the output data rate equals output data rate = ( f mod /64)/( n x fs ) where fs is the decimal equivalent of the code in the fs0 to fs9 bits and is in the range 1 to 1023, and fmod is the modulator frequency, which is equal to mclk/16. with a nominal mclk of 4.92 mhz, this results in a conversion rate from 4.69/n hz to 4.8/n khz, where n is the order of the sinc filter. ad7190 rev. 0 | page 22 of 40 table 18. operating modes md2 md1 md0 mode 0 0 0 continuous conversion mode (default). in continuous conv ersion mode, the adc continuously performs conversions and places the result in the data register. the dout/ rdy pin and the rdy bit in the status register go low when a conversion is complete. the user can read these conv ersions by setting the cread bit in the communications register to 1, which enables continuous read. when continuous read is enabled, the conversions are automatically placed on the dout line when sclk pulses are applied. alte rnatively, the user can instru ct the adc to output each conversion by writing to the communications register. after power-on, a reset, or a recon-figuration of the adc, the complete settling time of the filter is required to gene rate the first valid conversion. subsequent conversions are available at the selected output data rate, which is dependent on filter choice. 0 0 1 single conversion mode. when single conversion mode is selected, the adc powers up and performs a single conversion on the selected channel. the internal clock re quires up to 1 ms to power up and settle. the adc then performs the conversion, which requires the complete settling time of the filter. the conversion result is placed in the data register, rdy goes low, and the adc returns to power-down mode. the conversion remains in the data register and rdy remains active (low) until the data is read or another conversion is performed. 0 1 0 idle mode. in idle mode, the adc filter and modulator are he ld in a reset state even though the modulator clocks are still provided. 0 1 1 power-down mode. in power-down mode, all ad7190 circuitry, except the bridge power-down switch, is powered down. the bridge power-down switch remains active becaus e the user may need to power up the sensor prior to powering up the ad7190 for settling reasons. the ex ternal crystal, if selected, remains active. 1 0 0 internal zero-scale calibration. an internal short is automatically connected to the input. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 internal full-scale calibration. a full-scale input volt age is automatically connected to the input for this calibrati on. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full-scale coefficient is placed in the full-scale register of the selected channel. a full-scale calibration is required each time the gain of a channel is changed to minimize the full- scale error. 1 1 0 system zero-scale calibration. the user should connect th e system zero-scale input to the channel input pins as selected by the ch7 to ch0 bits in the configuration register. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is pl aced in idle mode following a calibration. the measured offset coefficient is placed in the offset register of the se lected channel. a system zero-scale calibration is required each time the gain of a channel is changed. 1 1 1 system full-scale calibration. the user should connect th e system full-scale input to the channel input pins as selected by the ch7 to ch0 bits in the configuration register. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is pl aced in idle mode following a calibration. the measured full-scale coefficient is placed in the full-scale register of the selected channel. a full-scale calibration is required each time the gain of a channel is changed. configuration register (rs2, rs1, rs0 = 0, 1, 0; power-on/reset = 0x000117) he coniguration register is a 2-bit register ro which data can be read or to which data can be written his register is u sed to conigure the dc or unipolar or bipolar ode, to enable or disable the buer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel able 1 outlines the bit designations or the ilter register co0 through co2 indicate the bit locations co denotes that the bit s are in the coniguration register co2 denotes the irst bit o the data strea he nuber in parentheses indicates the powe r-on/reset deault status o that bit ad7190 rev. 0 | page 23 of 40 con23 con22 con21 con20 con19 con18 con17 con16 chop(0) 0(0) 0(0) refsel(0) 0(0) 0(0) 0(0) (0) con15 con14 con13 con12 con11 con10 con9 con8 ch7(0) ch6(0) ch5(0) ch4(0) ch3(0) ch2(0) ch1(0) ch0(1) con7 con6 con5 con4 con3 con2 con1 con0 burn(0) refdet(0) 0(0) buf(1) u/ b (0) g2(1) g1(1) g0(1) table 19. configuration register bit designations bit location bit name description con23 chop chop enable bit. when the chop bit is cleared, chop is disabled. when the chop bit is set, chop is enabled. when chop is enabled, the offset and of fset drift of the adc are continuously minimized. however, this increases the conversion time and se ttling time of the adc. for example, when fs = 96 decimal and the sinc 4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. with chop disabled, higher conversion rates are allowed. for an fs word of 96 decimal and the sinc 4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. however, at low gains, periodic calibrations may be required to remove the offset and offset drift. con22, con21 these bits must be programmed with a logic 0 for correct operation. con20 refsel reference select bits. the reference source for the adc is selected using these bits. refsel reference voltage 0 external reference applied between refin1(+) and refin1( ? ). 1 external reference applied between the p1 and p0 pins. con19 to con16 these bits must be programmed with a logic 0 for correct operation. con15 to con8 ch7 to ch0 channel select bits. these bits are used to select which channels are enabled on the ad7190. see table 20 . several channels can be selected, and the ad7190 automatically sequences them. the conversion on each channel requires the complete settling time. con7 burn when this bit is set to 1 by the user, the 500 na cu rrent sources in the signal path are enabled. when burn = 0, the burnout currents are disabled. the burn out currents can be enabled only when the buffer is active and when chop is disabled. con6 refdet enables the reference detect function. when set, the noref bit in the status register indicates when the external reference being used by the adc is open circuit or less than 0.5 v typically. the reference detect circuitry only operates when the adc is active. con5 this bit must be programmed with a logic 0 for correct operation. con4 buf configures the adc for a buffered or an unbuffered mode of operation. if cleared, the adc operates in unbuffered mode, lowering the power consumption of the device. if set, the adc operates in buffered mode, allowing the user to place source impedances on the front end without co ntributing gain errors to the system. with the buffer disabled, the voltage on the analog input pins can be from 50 mv below gnd to 50 mv above av dd . when the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be limited to 250 mv within the power supply rails. con3 u/ b polarity select bit. when this bit is set, unipolar op eration is selected. when this bit is cleared, bipolar operation is selected. con2 to con0 g2 to g0 gain select bits. written by the user to select the adc input range as follows: g2 g1 g0 gain adc input range (5 v reference, bipolar mode) 0 0 0 1 + 5 v 0 0 1 reserved 0 1 0 reserved 0 1 1 8 + 625 mv 1 0 0 16 + 312.5 mv 1 0 1 32 + 156.2 mv 1 1 0 64 + 78.125 mv 1 1 1 128 + 39.06 mv ad7190 rev. 0 | page 24 of 40 table 20. channel selection channel enable bits in the configuration register channel enabled status register bits chd[3:0] calibration register pair ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 1 ain1 to ain2 0000 0 1 ain3 to ain4 0001 1 1 temperature sensor 0010 none 1 ain2 to ain2 0011 0 1 ain1 to aincom 0100 0 1 ain2 to aincom 0101 1 1 ain3 to aincom 0110 2 1 ain4 to aincom 0111 3 data register (rs2, rs1, rs0 = 0, 1, 1 power-on/reset = 0x000000) the conversion result from the adc is stored in this data register. this is a read-only, 24-bit register. on completion of a read operation from this register, the rdy pin/bit is set. when the dat_sta bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion. this is required when several analog input channels are enabled because the four lsbs of the status register (chd3 to chd0) identify the channel from which the conversion originated. gpocon register (rs2, rs1, rs0 = 1, 0, 1 power-on/reset = 0x00) the gpocon register is an 8-bit register from which data can be read or to which data can be written. this register is used to enable the general-purpose digital outputs. table 21 outlines the bit designations for the gpocon register. gp0 through gp7 indicate the bit locations. gp denotes that the bits are in the gpocon register. gp7 denotes the first bit of the data stream. the number in parentheses indicates the power-on/reset default status of that bit. ad7190 rev. 0 | page 25 of 40 gp7 gp6 gp5 gp4 gp3 gp2 gp1 gp0 0(0) bpdsw(0) gp32en(0) gp10en(0) p3dat(0) p2dat(0) p1dat(0) p0dat(0) table 21. register bit designations bit location bit name description gp7 0 this bit must be programmed with a logic 0 for correct operation. gp 6 bpdsw bridge power-down switch control bit. this bit is s et by the user to close the bridge power-down switch bpdsw to agnd. the switch can sink up to 30 ma. the bit is c leared by the user to open the bridge power- down switch. when the adc is placed in power-down mode, the bridge power-down switch remains active. gp5 gp32en digital output p3 and digital output p2 enable. when gp32en is set, the digital outputs, p3 and p2, are active. when gp32en is cleared, the p3 and p2 pins are tristated, and the p3dat and p2dat bits are ignored. gp4 gp10en digital output p1 and digital output p0 enable. when gp10en is set, the digital outputs, p1 and p0, are active. when gp10en is cleared, the p1 and p0 outp uts are tristated, and the p1dat and p0dat bits are ignored. the p1 and p0 pins can be used as a reference input refin2 when the refsel bit in the configuration register is set to 1. gp3 p3dat digital output p3. when gp32en is set, the p3dat bit se ts the value of the p3 general-purpose output pin. when p3dat is high, the p3 output pin is high. when p3dat is low, the p3 output pin is low. when the gpocon register is read, the p3dat bit reflects the status of the p3 pin; that is, a fault condition on the p3 pin is detected. gp2 p2dat digital output p2. when gp32en is set, the p2dat bit se ts the value of the p2 general-purpose output pin. when p2dat is high, the p2 output pin is high. when p2dat is low, the p2 output pin is low. when the gpocon register is read, the p2dat bit reflects the status of the p2 pin; that is, a fault condition on the p2 pin is detected. gp1 p1dat digital output p1. when gp10en is set, the p1dat bit se ts the value of the p1 general-purpose output pin. when p1dat is high, the p1 output pin is high. when p1dat is low, the p1 output pin is low. when the gpocon register is read, the p1dat bit reflects the status of the p1 pin; that is, a fault condition on the p1 pin is detected. gp0 p0dat digital output p0. when gp10en is set, the p0dat bit se ts the value of the p0 general-purpose output pin. when p0dat is high, the p0 output pin is high. when p0dat is low, the p0 output pin is low. when the gpocon register is read, the p0dat bit reflects the status of the p0 pin; that is, a fault condition on the p0 pin is detected. offset register (rs2, rs1, rs0 = 1, 1, 0 power-on/reset = 0x800000) the offset register holds the offset calibration coefficient for the adc. the power-on reset value of the offset register is 0x800000. the ad7190 has four offset registers therefore, each channel has a dedicated offset register. each of these registers is a 24-bit read/write register. this register is used in conjunction with its associated full-scale register to form a register pair. the power- on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. the ad7190 must be placed in power-down mode or idle mode when writing to the offset register. full-scale register (rs2, rs1, rs0 = 1, 1, 1 power-on/reset = 0x5xxxx0) the full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the adc. the ad7190 has four full- scale registers therefore, each channel has a dedicated full-scale register. the full-scale registers are read/write registers. however, when writing to the full-scale registers, the adc must be placed in power-down mode or idle mode. these registers are configured at power-on with factory-calibrated, full-scale calibration coef- ficients, the calibration being performed at gain = 1. therefore, every device has different default coefficients. the default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to. ad7190 rev. 0 | page 26 of 40 mclk1 mclk2 p0/refin2(?) p1/refin2(+) dv dd dgnd 5 adc circuit information v ain1 in+ in? out? out+ ain2 ain3 ain4 aincom refin1(?) bpdsw agnd ad7190 refin1(+) reference detect serial interface and control logic temp sensor clock circuitry av dd agnd av dd agnd dout/rdy din sclk cs sync p3 p2 - adc pga mux 0 7640-012 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 255075100125150 filter gain (db) frequency (hz) figure 18. basic connection diagram overview the ad7190 is an ultralow noise adc that incorporates a - modulator, a buffer, pga, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain gauge applications. the part can be configured to have two differential inputs or four pseudo differential inputs that can be buffered or unbuffered. figure 18 shows the basic connections required to operate the part. filter, output data rate, settling time a - adc consists of a modulator followed by a digital filter. the ad7190 has two filter options: a sinc 3 filter and a sinc 4 filter. the filter is selected using the sinc3 bit in the mode register. when sinc3 is set to 0 (default value), the sinc 4 filter is selected. the sinc 3 filter is selected when sinc3 is set to 1. at low update rates (<1 khz), the noise-free resolution is comparable for the two filter types. however, at the higher update rates, the sinc 4 filter gives better noise free resolution. the sinc 4 filter also leads to better 50 hz and 60 hz rejection. while the notch positions are not affected by the order of the filter, the higher order filter has wider notches, which leads to better rejection in the band (1 hz) around the notches. it also gives better stop-band attenuation. the benefit of the sinc 3 filter is its lower settling time for the same output data rate. chop disabled the output data rate (the rate at which conversions are available on a single channel when the adc is continuously converting) is equal to f adc = f clk /(1024 fs [9:0]) where: f adc is the output data rate. f clk = master clock (4.92 mhz nominal). fs[ 9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. the output data rate can be programmed from 4.7 hz to 4800 hz; that is, fs [9:0] can have a value from 1 to 1023. the above equation is valid for both the sinc 3 and sinc 4 filters. the settling time for the sinc 4 filter is equal to t settle = 4/ f adc whereas the settling time for the sinc 3 filter is equal to t settle = 3/ f adc figure 19 and figure 20 show the frequency response of the sinc 4 and sinc 3 filters, respectively, for an output data rate of 50 hz. 07640-013 figure 19. sinc 4 filter response (50 hz output data rate) ad7190 rev. 0 | page 27 of 40 ?90 ?100 0 255075100125150 frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 filter gain (db) 07640-014 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 255075100125150 filter gain (db) frequency (hz) figure 20. sinc 3 filter response (50 hz output data rate) as shown in the plots, the sinc 4 filter provides 50 hz (1 hz) rejection in excess of 120 db, assuming a stable master clock, while the sinc 3 filter gives a rejection of 100 db. the stop-band attenuation is typically 53 db for the sinc 4 filter but equal to 40 db for the sinc 3 filter. the 3 db frequency for the sinc 4 filter is equal to f 3db = 0.23 f adc and for the sinc 3 filter is equal to f 3db = 0.272 f adc chop enabled with chop enabled, the analog input offset and offset drift are minimized. when chop is enabled, the analog input pins are continuously swapped. therefore, with the analog input pins connected in one direction, the settling time of the sinc filter is allowed to elapse until a valid conversion is available. the analog input pins are then inverted and another valid conversion is obtained. subsequent conversions are then averaged so that the offset is minimized. this continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. chopping affects the output data rate and settling time of the adc. for the sinc 4 filter, the output data rate is equal to f adc = f clk /(4 x 1024 fs [9:0]) for sinc 3 filter, the output data rate is equal to f adc = f clk /(3 x 1024 fs [9:0]) where: f adc is the output data rate. f clk = master clock (4.92 mhz nominal). fs [9:0] is the decimal equivalent of bit fs9 to bit fs0 in the mode register. the value of fs [9:0] can be varied from 1 to 1023. this results in an output data rate of 1.173 hz to 1200 hz for the sinc 4 filter and 1.56 hz to 1600 hz for the sinc 3 filter. the settling time for the sinc 3 or sinc 4 filter is equal to t settle = 2/ f adc therefore, with chop enabled, the settling time is reduced for a given output data rate compared to the chop disabled mode. for either the sinc 3 or the sinc 4 filter, the cutoff frequency f 3db is equal to f 3db = 0.24 f adc figure 21 and figure 22 show the filter response for the sinc 4 and sinc 3 filters, respectively, when chop is enabled. as shown in the plots, the stop-band attenuation is less compared with the chop disabled modes. 07640-015 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 255075100125150 filter gain (db) frequency (hz) figure 21. sinc 4 filter response (output data rate = 12.5 hz, chop enabled) 07640-016 figure 22. sinc 3 filter response (output data rate = 16.6 hz, chop enabled) ad7190 rev. 0 | page 28 of 40 ?90 50 hz/60 hz rejection normal mode rejection is one of the main functions of the digital filter. with chop disabled, 50 hz rejection is obtained when the output data rate is set to 50 hz, whereas 60 hz rejection is achieved when the output data rate is set to 60 hz. simul-taneous 50 hz and 60 hz rejection is obtained when the output data rate is set to 10 hz. simultaneous 50 hz/60 hz rejection can also be achieved using the rej60 bit in the mode register. when the output data rate is programmed to 50 hz and the rej60 bit is set to 1, notches are placed at both 50 hz and 60 hz. figure 23 and figure 24 show the frequency response of the sinc 4 and sinc 3 filters, respectively, when the output data rate is programmed to 50 hz and rej60 is set to 1. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 filter gain (db) ?100 0 255075100125150 frequency (hz) 07640-017 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 filter gain (db) figure 23. sinc 4 filter response (50 hz output data rate, rej60 = 1) ?90 ?100 0 255075100125150 frequency (hz) 07640-018 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 255075100125150 filter gain (db) frequency (hz) figure 24. sinc 3 filter response (50 hz output data rate, rej60 = 1) again, the sinc 4 filter provides better 50 hz/60 hz rejection than the sinc 3 filter. in addition, better stop-band attenuation is achieved with the sinc 4 filter. when chop is enabled, lower output data rates must be used to achieve 50 hz and 60 hz rejection. an output data rate of 12.5 hz gives simultaneous 50 hz/60 hz rejection when the sinc 4 filter is selected, whereas an output data rate of 16.7 hz gives simultaneous 50 hz/ 60 hz rejection when the sinc 3 filter is used. setting the rej60 bit at these output data rates further improves the rejection at 60 hz. figure 25 and figure 26 show the filter response for both output data rates when rej60 is set to 1. 07640-125 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 255075100125150 filter gain (db) frequency (hz) figure 25. sinc 4 filter response (12.5 hz output data rate, chop enabled, rej60 = 1) 07640-126 figure 26. sinc 3 filter response (16.7 hz output data rate, chop enabled, rej60 = 1) channel sequencer the ad7190 includes a channel sequencer, which simplifies communications with the device in multichannel applications. bis ch0 to bit ch7 in the configuration register are used to enable the required channels. in continuous conversion mode, the adc selects each of the enabled channels in sequence and performs a conversion on the channel. the rdy pin goes low when a valid conversion is available on each channel. when several channels are enabled, the contents of the status register should be attached to the 24-bit word so that the user can identify the channel that corresponds to each conversion. to attach the status register value to the conversion, bit dat_sta in the mode register should be set to 1. when several channels are enabled, the adc must allow the complete settling time to generate a valid conversion each time that the channel is changed. the ad7190 takes care of this: when a channel is selected, the modulator and filter are reset ad7190 rev. 0 | page 29 of 40 and the rdy pin is taken high. the ad7190 then allows the complete settling time to generate the first conversion. rdy only goes low when a valid conversion is available. the ad7190 then selects the next enabled channel and converts on that channel. the user can then read the data register while the adc is performing the conversion on the next channel. the frequency at which all enabled channels are converted is equal to t settle number of enabled channels for example, if the sinc 4 filter is selected, chop is disabled and zero latency is disabled, conversions are available at 1/f adc when converting on a single channel, where f adc is equal to the output data rate. the settling time is equal to 07640-019 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0100 50 200 300 400 500 150 250 350 450 550 600 filter gain (db) frequency (hz) 07640-020 t settle = 4/f adc the time required to sample n channels is 4/( f adc n ) rdy conversions channel a channel b 1/f adc channel c figure 27. channel sequencer zero latency zero latency is enabled by setting the single bit in the mode register to 1. with zero latency, the complete settling time is allowed for each conversion. therefore, f adc = 1/ t settle zero latency means that the output data rate is constant irrespective of the number of analog input channels enabled; the user does not need to consider the effects of channel changes on the output data rate. the disadvantages of zero latency are the increased noise for a given output data rate compared with the nonzero latency mode. for example, when zero latency is not enabled, the ad7190 has a noise-free resolution of 18.5 bits when the output data rate is 50 hz and the gain is set to 128. when zero latency is enabled, the adc has a resolution of 17.5 bits peak-to-peak when the output data rate is 50 hz. the filter response also changes. figure 19 shows the filter response for the sinc 4 filter when the output data rate is 50 hz (zero latency disabled). figure 28 shows the filter response when zero latency is enabled and the output data rate is 50 hz (sinc 4 filter); 50 hz rejection is no longer achieved. the adc needs to operate with an output data rate of 12.5 hz to obtain 50 hz rejection when zero latency is enabled. to obtain simultaneous 50 hz/60 hz rejection, the rej60 bit in the mode register can be set when the output data rate is equal to 12.5 hz. the stop-band attenuation is considerably reduced also (3 db compared with 53 db in the nonzero latency mode). figure 28. sinc 4 filter response (50 hz output data rate, zero latency) digital interface as indicated in the on-chip registers section, the programmable functions of the ad7190 are controlled using a set of on-chip registers. data is written to these registers via the serial interface of the part. read access to the on-chip registers is also provided by this interface. all communication with the part must start with a write to the communications register. after power-on or reset, the device expects a write to its communications register. the data written to this register determines whether the next operation is a read operation or a write operation and also determines which register this read or write operation affects. therefore, write access to any of the other registers on the part begins with a write operation to the communications register, followed by a write to the selected register. a read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. the serial interface of the ad7190 consists of four signals: cs , din, sclk, and dout/ rdy . the din line is used to transfer data into the on-chip registers, whereas dout/ rdy is used for accessing data from the on-chip registers. sclk is the serial clock input for the device, and all data transfers (either on din or dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin functions as a data ready signal also, the line going low when a new data-word is available in the output register. it is reset high when a read operation from the data register is complete. it also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated. cs is used to select a device. it can be used to decode the ad7190 in systems where several components are connected to the serial bus. ad7190 rev. 0 | page 30 of 40 figure 3 and figure 4 show timing diagrams for interfacing to the ad7190, with cs being used to decode the part. shows the timing for a read operation from the output shift register of the ad7190, and shows the timing for a write operation to the input shift register. it is possible to read the same word from the data register several times even though the dout/ figure 3 figure 4 rdy line returns high after the first read operation. however, care must be taken to ensure that the read operations have been com- pleted before the next output update occurs. in continuous read mode, the data register can be read only once. the ad7190 can be configured to continuously convert or to perform a single conversion. see figure 29 through figure 31 . single conversion mode in single conversion mode, the ad7190 is placed in power- down mode after conversions. when a single conversion is initiated by setting md2, md1, and md0 to 0, 0, 1, respectively, in the mode register, the ad7190 powers up, performs a single conversion, and then returns to power-down mode. the on- chip oscillator requires 1 ms approximately to power up. dout/ rdy goes low to indicate the completion of a conversion. when the data word has been read from the data register, dout/ rdy goes high. if cs is low, dout/ rdy remains high until another conversion is initiated and completed. the data register can be read several times, if required, even when dout/ rdy has gone high. the serial interface can operate in 3-wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy lines are used to communicate with the ad7190. the end of the conversion can be monitored using the rdy bit or pin. this scheme is suitable for interfacing to microcontrollers. if cs is required as a decoding signal, it can be generated from a port pin. for microcontroller interfaces, it is recommended that sclk idle high between data transfers. if several channels are enabled, the adc sequences through the enabled channels and performs a conversion on each channel. when a conversion is started, dout/ rdy goes high and remains high until a valid conversion is available. as soon as the conversion is available, dout/ rdy goes low. the adc then selects the next channel and begins a conversion. the user can read the present conversion while the next conversion is being performed. as soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. when the adc has performed a single conversion on each of the selected channels, it returns to power-down mode. the ad7190 can be operated with cs used as a frame synchron- ization signal. this scheme is useful for dsp interfaces. in this case, the first bit (msb) is effectively clocked out by cs because cs normally occurs after the falling edge of sclk in dsps. the sclk can continue to run between data transfers, provided the timing numbers are obeyed. the serial interface can be reset by writing a series of 1s to the din input. if a logic 1 is written to the ad7190 din line for at least 40 serial clock cycles, the serial interface is reset. this ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. reset returns the interface to the state in which it is expecting a write to the communications register. this operation resets the contents of all registers to their power-on values. following a reset, the user should allow a period of 500 s before addressing the serial interface. if the dat_sta bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. the four lsbs of the status register indicate the channel to which the conversion corresponds. cs 0x08 0x58 data 0x280060 din sclk dout/rdy 07640-021 figure 29. single conversion ad7190 rev. 0 | page 31 of 40 continuous conversion mode continuous conversion is the default power-up mode. the ad7190 converts continuously, the rdy bit in the status register going low each time a conversion is complete. if cs is low, the dout/ rdy line also goes low when a conversion is completed. to read a conversion, the user writes to the com- munications register, indicating that the next operation is a read of the data register. the digital conversion is placed on the dout/ rdy pin as soon as sclk pulses are applied to the adc. dout/ rdy returns high when the conversion is read. the user can read this register additional times, if required. however, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word is lost. when several channels are enabled, the adc continuously loops through the enabled channels, performing one conversion on each channel per loop. the data register is updated as soon as each conversion is available. the dout/ rdy pin pulses low each time a conversion is available. the user can then read the conversion while the adc converts on the next enabled channel. if the dat_sta bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. the status register indicates the channel to which the conversion corresponds. cs din dout/rdy 0x58 0x58 data data sclk 07640-022 figure 30. continuous conversion ad7190 rev. 0 | page 32 of 40 continuous read rather than write to the communications register each time a conversion is complete to access the data, the ad7190 can be configured so that the conversions are placed on the dout/ rdy line automatically. by writing 01011100 to the commun- ications register, the user need only apply the appropriate number of sclk cycles to the adc, and the conversion word is automatically placed on the dout/ rdy line when a conversion is complete. the adc should be configured for continuous conversion mode. when dout/ rdy goes low to indicate the end of a conversion, sufficient sclk cycles must be applied to the adc; the data conversion is then placed on the dout/ rdy line. when the conversion is read, dout/ rdy returns high until the next conversion is available. in this mode, the data can be read only once. also, the user must ensure that the data-word is read before the next conversion is complete. if the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the ad7190 to read the word, the serial output register is reset when the next conversion is complete and the new conversion is placed in the output serial register. to exit the continuous read mode, the instruction 01011000 must be written to the communications register while the rdy pin is low. while in the continuous read mode, the adc monitors activity on the din line so that it can receive the instruction to exit the continuous read mode. additionally, a reset occurs if 40 consecutive 1s are seen on din. therefore, din should be held low in continuous read mode until an instruction is to be written to the device. when several channels are enabled, the adc continuously steps through the enabled channels and performs one con- version on each channel each time that it is selected. dout/ rdy pulses low when a conversion is available. when the user applies sufficient sclk pulses, the data is automatically placed on the dout/ rdy pin. if the dat_sta bit in the mode register is set to 1, the contents of the status register are output along with the conversion. the status register indicates the channel to which the conversion corresponds. din sclk dout/rdy cs 0x5c data data data 7640-023 0 figure 31. continuous read ad7190 rev. 0 | page 33 of 40 circuit description analog input channel the ad7190 has two differential/four pseudo differential analog input channels which can be buffered or unbuffered. in buffered mode (the buf bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gauges or resistance temperature detectors (rtds). when buf = 0, the part is operated in unbuffered mode. this results in a higher analog input current. note that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the adc input. table 22 shows the allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20-bit level is introduced. table 22. external r-c combination for no 20-bit gain error c (pf) r () 50 1.4 k 100 850 500 300 1000 230 5000 30 the absolute input voltage range in buffered mode is restricted to a range between agnd + 250 mv and av dd C 250 mv. care must be taken in setting up the common-mode voltage so that these limits are not exceeded. otherwise, there is degradation in linearity and noise performance. the absolute input voltage in unbuffered mode includes the range between agnd C 50 mv and av dd + 50 mv. the negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to gnd. pga when the gain stage is enabled, the output from the buffer is applied to the input of the programmable gain array (pga). the presence of the pga means that signals of small amplitude can be gained within the ad7190 while still maintaining excel- lent noise performance. for example, when the gain is set to 128, the rms noise is 8.5 nv, typically, when the output data rate is 4.7 hz, which is equivalent to 23 bits of effective resolution or 20.5 bits of noise-free resolution. the ad7190 can be programmed to have a gain of 1, 8, 16, 32, 64, and 128 using bit g2 to bit g0 in the configuration register. therefore, with an external 2.5 v reference, the unipolar ranges are from 0 mv to 19.53 mv to 0 v to 2.5 v, and the bipolar ranges are from 19.53 mv to 2.5 v. the analog input range must be limited to (av dd ? 1.25 v)/gain because the pga requires some headroom. therefore, if v ref = av dd = 5 v, the maximum analog input that can be applied to the ad7190 is 0 to 3.75 v/gain in unipolar mode or 3.75 v/ gain in bipolar mode. bipolar/unipolar configuration the analog input to the ad7190 can accept either unipolar or bipolar input voltage ranges. a bipolar input range does not imply that the part can tolerate negative voltages with respect to system gnd. unipolar and bipolar signals on the ain(+) input are referenced to the voltage on the ain(?) input. for example, if ain( ? ) is 2.5 v and the adc is configured for unipolar mode with a gain of 1, the input voltage range on the ain(+) pin is 2.5 v to 5 v when a 2.5 v reference is used. if the adc is configured for bipolar mode, the analog input range on the ain(+) input is 0 v to 5 v. the bipolar/unipolar option is chosen by programming the u/ b bit in the configur- ation register. data output coding when the adc is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a midscale voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. the output code for any analog input voltage can be represented as code = (2 n ain gain )/ v ref when the adc is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. the output code for any analog input voltage can be represented as code = 2 n C 1 [( ain gain / v ref ) + 1] where ain is the analog input voltage, gain is the pga setting (1 to 128), and n = 24. clock the ad7190 includes an internal 4.92 mhz clock on-chip. this internal clock has a tolerance of 4%. either the internal clock or an external crystal/clock can be used as the clock source to the ad7190. the clock source is selected using the clk1 and clk0 bits in the mode register. when an external crystal is used, it must be connected across the mclk1 and mclk2 pins. the crystal manufacturer recommends the load capaci- tances required for the crystal. the mclk1 and mclk2 pins of the ad7190 have a capacitance of 15 pf, typically. if an external clock source is used, the clock source must be connected to the mclk2 pin and the mclk1 pin must be left floating. ad7190 rev. 0 | page 34 of 40 the internal clock can also be made available at the mclk2 pin. this is useful when several adcs are used in an application and the devices need to be synchronized. the internal clock from one device can be used as the clock source for all adcs in the system. using a common clock, the devices can be syn- chronized by applying a common reset to all devices, or the sync pin can be pulsed. burnout currents the ad7190 contains two 500 na constant current generators, one sourcing current from av dd to ain(+) and one sinking current from ain(?) to gnd. the currents are switched to the selected analog input pair. both currents are either on or off, depending on the burnout current enable (burn) bit in the configuration register. these currents can be used to verify that an external transducer remains operational before attempting to take measurements on that channel. after the burnout currents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. if the resultant voltage measured is full scale, the user needs to verify why this is the case. a full-scale reading could mean that the front-end sensor is open circuit. it could also mean that the front-end sensor is overloaded and is justified in outputting full scale, or the reference may be absent and the noref bit in the status register is set, thus clamping the data to all 1s. when reading all 1s from the output, the user needs to check these three cases before making a judgment. if the voltage measured is 0 v, it may indicate that the transducer has short circuited. the current sources work over the normal absolute input voltage range specifications when the analog inputs are buffered and chop is disabled. reference the adc has a fully differential input capability for the refer- ence channel. in addition, the user has the option of selecting one of two external reference options (refin1(x) or refin2(x)). the reference source for the ad7190 is selected using the refsel bit in the configuration register. the refin2(x) pins are dual purpose: they can function as two general-purpose output pins or as reference pins. when the refsel bit is set to 1, these pins automatically function as reference pins. the common-mode range for these differential inputs is from gnd to av dd . the reference input is unbuffered; therefore, excessive r-c source impedances introduce gain errors. the reference voltage refin (refinx(+) ? refinx(?)) is av dd nominal, but the ad7190 is functional with reference voltages from 1 v to av dd . in applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. if the ad7190 is used in a nonratiometric applica- tion, use a low noise reference. recommended 2.5 v reference voltage sources for the ad7190 include the adr421 and adr431 , which are low noise references. also note that the reference inputs provide a high impedance, dynamic load. because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source driving the reference inputs. reference voltage sources like those recommended above (for example, adr431 ) typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on refinx(+) without introducing gain errors in the system. deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. external decoupling on the refinx pins is not recommended in this type of circuit configuration. reference detect the ad7190 includes on-chip circuitry to detect whether the part has a valid reference for conversions or calibrations. this feature is enabled when the refdet bit in the configuration register is set to 1. if the voltage between the selected refinx(+) and refinx(C) pins goes below 0.3 v or either the refinx(+) or refinx(C) input is open circuit, the ad7190 detects that it no longer has a valid reference. in this case, the noref bit of the status register is set to 1. if the ad7190 is performing normal conversions and the noref bit becomes active, the conversion results is all 1s. therefore, it is not necessary to continuously monitor the status of the noref bit when performing conversions. it is only necessary to verify its status if the con- version result read from the adc data register is all 1s. if the ad7190 is performing either an offset or full-scale calibration and the noref bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the err bit in the status register is set. if the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the err bit should be checked at the end of the calibration cycle. reset the circuitry and serial interface of the ad7190 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. this resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. a reset is automatically performed on power-up. when a reset is initiated, the user must allow a period of 500 s before accessing any of the on- chip registers. a reset is useful if the serial interface becomes asynchronous due to noise on the sclk line. ad7190 rev. 0 | page 35 of 40 system synchronization the sync input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. this allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of sync . sync needs to be taken low for four master clock cycles to implement the synchronization function. if multiple ad7190 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. a falling edge on the sync pin resets the digital filter and the analog modulator and places the ad7190 into a consistent, known state. while the sync pin is low, the ad7190 is maintained in this state. on the sync rising edge, the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again. in a system using multiple ad7190 devices, a common signal to their sync pins synchronizes their operation. this is normally done after each ad7190 has performed its own calibration or has had calibration coefficients loaded into its calibration registers. the conversions from the ad7190s are then synchronized. the part is taken out of reset on the master clock falling edge following the sync low to high transition. therefore, when multiple devices are being synchronized, the sync pin should be taken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. if the sync pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle. the sync pin can also be used as a start conversion command. in this mode, the rising edge of sync starts conversion, and the falling edge of rdy indicates when the conversion is complete. the disadvantage of this scheme is that the settling time of the filter has to be allowed for each data register update. this means that the rate at which the data register is updated is reduced. for example, if the adc is configured to use the sinc 4 filter, zero latency is disabled and chop is disabled, the data register update takes four times longer. temperature sensor embedded in the ad7190 is a te mperature sensor. this is selected using the ch2 bit in the configuration register. when the ch2 bit is set to 1, the temperature sensor is enabled. when the temperature sensor is selected and bipolar mode is selected, the device should return a co de of 0x800000 when the temper- ature is 0 k. a one-point calibration is needed to get the opti- mum performance from the sensor. therefore, a conversion at a known temperature should be recorded. using this point along with the 0 k point, the gain error can be calculated. the sensitivity is 2815 codes/c, typically. the equation for the temperature sensor is temp (k) = ( conversion C 0x800000)/2815 k temp (c) = temp (k) C 273 following the one point calibrat ion, the internal temperature sensor has an accuracy of 2 c, typically. bridge power-down switch in bridge applications such as strain gauges and load cells, the bridge itself consumes the majority of the current in the system. for example, a 350 load cell requires 15 ma of current when excited with a 5 v supply. to minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the bridge power-down switch. figure 18 shows how the bridge power-down switch is used. the switch can withstand 30 ma of continuous current, and it has an on resistance of 10 maximum. logic outputs the ad7190 has four general-purpose digital outputs, p0, p1, p2, and p3. these are enabled using the gp32en and gp10en bits in the gpocon register. the pins can be pulled high or low using the p0dat to p3dat bits in the gpocon register; that is, the value at the pin is determined by the setting of the p0dat to p3dat bits. the logic levels for these pins are determined by av dd rather than by dv dd . when the gpocon register is read, the bits p0dat to p3dat reflect the actual value at the pins. this is useful for short-circuit detection. these pins can be used to drive external circuitry, for example, an external multiplexer. if an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled via the ad7190 general-purpose output pins. the general-purpose output pins can be used to select the active multiplexer pin. because the operation of the multiplexer is independent of the ad7190, the ad7190 modulator and filter should be reset using the sync pin each time that the multi- plexer channel is changed. enable parity the ad7190 also has a parity check function on-chip that detects 1-bit errors in the serial communications between the adc and the microprocessor. when the enpar bit in the mode register is set to 1, parity is enabled. the contents of the status register must be transmitted along with each 24-bit conversion when the parity function is enabled. to append the contents of the status register to each conversion read, the dat_sta bit in the mode register should be set to 1. for each conversion read, the parity bit in the status register is programmed so that the overall number of 1s transmitted in the 24-bit data-word is even. therefore, for example, if the 24-bit conversion contains eleven 1s (binary format), the parity bit is set to 1 so that the total number of 1s in the serial transmission is even. if the microprocessor receives an odd number of 1s, it knows that the data received has been corrupted. ad7190 rev. 0 | page 36 of 40 the parity function only detects 1-bit errors. for example, two bits of corrupt data can result in the microprocessor receiving an even number of 1s. therefore, an error condition is not detected. calibration the ad7190 provides four calibration modes that can be pro- grammed via the mode bits in the mode register. these modes are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration. a calibration can be performed at any time by setting the md2 to md0 bits in the mode register appropriately. a calibration should be performed when the gain is changed. after each conversion, the adc conversion result is scaled using the adc calibration registers before being written to the data register. the offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient. to start a calibration, write the relevant value to the md2 to md0 bits. the dout/ rdy pin and the rdy bit in the status register go high when the calibration is initiated. when the calibration is complete, the contents of the corresponding calibration registers are updated, the rdy bit in the status register is reset, the dout/ rdy pin returns low (if cs is low), and the ad7190 reverts to idle mode. during an internal zero-scale or full-scale calibration, the res- pective zero input and full-scale input are automatically connected internally to the adc input pins. a system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the adc pins before initiating the calibration mode. in this way, external adc errors are removed. from an operational point of view, treat a calibration like another adc conversion. a zero-scale calibration, if required, must always be performed before a full-scale calibration. set the system software to monitor the rdy bit in the status register or the dout/ rdy pin to determine the end of calibration via a polling sequence or an interrupt-driven routine. with chop disabled, both an internal zero-scale calibration and a system zero-scale calibration require a time equal to the settling time, t settle , (4/f adc for the sinc 4 filter and 3/f adc for the sinc 3 filter). with chop enabled, an internal zero-scale calibration is not needed because the adc itself minimizes the offset continuously. however, if an internal zero-scale calibration is performed, the settling time, t settle, (2/f adc ) is required to perform the calibra- tion. similarly, a system zero-scale calibration requires a time of t settle to complete. to perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. for a gain of 1, the time required for an internal full-scale calibration is equal to t settle . for higher gains, the internal full-scale calibration requires a time of 2 t settle . a full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error. a system full-scale calibration requires a time of t settle . with chop disabled, the zero-scale calibration (internal or system zero-scale) should be performed before the system full-scale calibration is initiated. an internal zero-scale calibratio n, system zero-scale calibration and system full-scale calibration can be performed at any output data rate. an internal full-scale calibration can be performed at any output data rate for which the filter word fs[9:0] is divisible by 16, fs[9:0] being the decimal equivalent of the 10-bit word written to bit fs9 to bit fs0 in the mode register. therefore, internal full-scale calibrations can be performed at output data rates such as 300 hz, 150 hz, and 100 hz. using these lower output data rates results in better calibration accuracy. the gain error of the ad7190 is factory calibrated at a gain of 1 with a 5 v power supply at ambient temperature. following this calibration, the gain error is 0.001%, typically, at 5 v. the offset error is, typically, 100 v/gain. if the gain is changed, it is advisable to perform a calibration. a zero-scale calibration (an internal zero-scale calibration or system zero-scale calibration) reduces the offset error to the order of the noise. table 23 shows the uncalibrated gain error for the different gain settings. an internal full-scale calibration reduces the gain error to 0.001%, typically, when the gain is equal to 1. for higher gains, the gain error post internal full-scale calibration is 0.0075%, typically. a system full-sale calibration reduces the gain error to the order of the noise. table 23. precalibration gain error vs. gain gain precalibration gain error (%) 8 ?0.11 16 ?0.20 32 ?0.23 64 ?0.29 128 ?0.39 the ad7190 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the eeprom. a read of the registers can be performed at any time. however, the adc must be placed in power-down or idle mode when writing to the registers. the values in the calibration registers are 24-bits wide. the span and offset of the part can also be manipulated using the registers. grounding and layout because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are common- mode voltages. the high common-mode rejection of the part removes common-mode noise on these inputs. the analog and digital supplies to the ad7190 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter provides rejection of broadband noise on the power supplies, except at ad7190 rev. 0 | page 37 of 40 integer multiples of the modulator sampling frequency. connect an r-c filter to each analog input pin to provide rejection at the modulator sampling frequency. a 100 resistor in series with each an alog input (a 0.1 f capacitor from ainx(+) to ainx(?) along with a 0.01 f capacitor from each analog input to agnd) is advised. the digital filter also removes noise from the analog and reference inputs provided these noise sources do not satura te the analog modulator. as a result, the ad7190 is more immune to noise interference than a conventional high resolution converter. however, because the resolution of the ad7190 is so high and the noise levels from the converter so low, care must be taken with regard to grounding and layout. the printed circuit board (pcb) that houses the adc must be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes because it gives the best shielding. although the ad7190 has separate pins for analog and digital ground, the agnd and dgnd pins are tied together internally via the substrate. therefore, the user must not tie these two pins to separate ground planes unless the ground planes are connected together near the ad7190. in systems in which the ag nd and dgnd are connected somewhere else in the system (that is, the power supply of the system), they should not be connected again at the ad7190 because a ground loop results. in these situations, it is recommended that ground pins of the ad7190 be tied to the agnd plane. in any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destin- ations. avoid forcing digital curr ents to flow through the agnd. avoid running digital lines under the device because this couples noise onto the die, a nd allow the analog ground plane to run under the ad7190 to prev ent noise coupling. the power supply lines to the ad7190 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board, and never run clock signals near the analog inputs. avoid crossover of digital and analog signals. run traces on opposite sides of the board at right angles to each other. this reduces the effect s of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. good decoupling is important when using high resolution adcs. decouple all analog supplies with 10 f tantalum in parallel with 0.1 f capacitors to agnd. to achieve the best from these decoupling components, place them as close as possible to the device, ideally right up against th e device. decouple all logic chips with 0.1 f ceramic capacitors to dgnd. in systems in which a common supply voltage is used to drive both the av dd and dv dd of the ad7190, it is recommended that the system av dd supply be used. for this supply, plac e the recommended analog supply decoupling capacitors between the av dd pin of the ad7190 and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the ad7190 and dgnd. ad7190 rev. 0 | page 38 of 40 mclk1 mclk2 p0/refin2(?) p1/refin2(+) dv dd dgnd 5 applications information the ad7190 provides a low-cost, high resolution analog-to- digital function. because the analog-to-digital function is provided by a - architecture, it makes the part more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. weigh scales figure 32 shows the ad7190 being used in a weigh scale application. the load cell is arranged in a bridge network and gives a differential output voltage between its out+ and outC terminals. assuming a 5 v excitation voltage, the full-scale output range from the transducer is 10 mv when the sensitivity is 2 mv/v. the excitation voltage for the bridge can be used to directly provide the reference for the adc because the reference input range includes the supply voltage. a second advantage of using the ad7190 in transducer-based applications is that the bridge power-down switch can be fully utilized to minimize the power consumption of the system. the bridge power-down switch is connected in series with the cold side of the bridge. in normal operation, the switch is closed and measurements can be taken. in applications in which current consumption is being minimized, the ad7190 can be placed in standby mode, thus significantly reducing the power consumed in the application. in addition, the bridge power-down switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front-end transducer. when the part is taken out of standby mode and the bridge power-down switch is closed, the user should ensure that the front-end circuitry is fully settled before attempting a read from the ad7190. for simplicity, external fi lters are not included in figure 32 . however, an r-c antialias filter should be included on each analog input. this is required because the on-chip digital filter does not provide any rejection around the modulator sampling frequency or multiples of this frequency. suitable values are a 100 resistor in series with each analog input, a 0.1 f capa- citor from ainx(+) to ainx(?), and 0.01 f capacitors from ainx(+)/ainx(?) to agnd. v ain1 in+ in? out? out+ ain2 ain3 ain4 aincom refin1(?) bpdsw agnd ad7190 refin1(+) reference detect serial interface and control logic temp sensor clock circuitry av dd agnd av dd agnd dout/rdy din sclk cs sync p3 p2 - adc pga mux 0 7640-024 figure 32. typical application (weigh scale) ad7190 rev. 0 | page 39 of 40 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 33. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide models temperature range package description package option ad7190bruz 1 C40c to +105c 24-lead tssop ru-24 ad7190bruz-reel 1 C40c to +105c 24-lead tssop ru-24 1 z = rohs compliant part. ad7190 rev. 0 | page 40 of 40 ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07640-0-10/08(0) notes |
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